1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and, more particularly, to a nonvolatile semiconductor memory device realizing reduction in its circuit size.
2. Description of Related Art
There are various semiconductor integrated circuits each having a nonvolatile semiconductor memory device for holding various setting values. FIG. 7 is an internal block diagram of a conventional nonvolatile semiconductor memory device. Each of word lines W1 to W4 constructing a memory array is connected to a negative voltage applying circuit NEG for applying negative voltage at the time of erasure. An erase voltage applying circuit ED applies positive voltage at the time of erasure and, in reading/writing operation, connects a common source line CS to the ground potential 0V of the circuit. Next, an erasing operation will be described. The erasing operation is formed by applying negative voltage to the control gate of a memory cell and positive voltage to the source and moving electrons held in a floating gate by the potential difference between the positive and negative voltages to the source region by Fowler-Nordheim tunnel emission. To the erase voltage applying circuit ED and negative voltage applying circuit NEG, power source voltage Vcc is supplied as an operating voltage.
As techniques related to the above, Japanese Patent Application Laid-open Nos. 2002-118187 and 2002-83872 are disclosed.